In this invention, an approach is employed as the premise to once write a luminance signal in a composite video signal CS into a video memory as video data thereafter to read out the video data for a second time to display it on a monitor. On this premise, by carrying out an address control in a write/read operation of video data with respect to the video memory, expansion/contraction in a vertical direction of an image is attained.
FIG. 1 is a block diagram showing a conventional video processor. A PLL (Phase Locked Loop) circuit 9 is a circuit adapted for generating a line clock signal for incrementing an address in a vertical direction of a video memory 7. To a reference input terminal 1(a) of a phase comparator 1 in the PLL circuit 9, a vertical synchronizing signal separated and extracted from a composite video signal CS is inputted. A signal outputted from the phase comparator 1 is applied to a VCO (Voltage Controlled Oscillator) 3 through a loop filter 2. The VCO 3 generates a clock signal having a frequency corresponding to its input signal voltage. This clock signal is used as a vertical line clock signal for video memory 7. This clock signal outputted from VCO3 is frequency-divided by M at a frequency divider 8. The frequency-divided signal thus obtained is fed back to a phase comparison input terminal 1(b) of the phase comparator 1. By employing such a configuration, a line clock signal CK having a period Tx synchronous in phase with the vertical synchronizing signal is obtained (It is to be noted that the period Tx is expressed as Tx=Tv/M; Tv is a period of the vertical synchronizing signal).
In the above-described conventional video processor, by allowing the frequency-dividing ratio M value of the frequency divider 8 to have several tens to several thousands of lock ranges (upper limit/lower limit frequency variable widths of a frequency in a lock state), expansion (enlargement) or contraction in a vertical direction is realized. However, generally, in the case where a PLL circuit is used, it is stable minimum range to set the width of lock ranges in which ratio of maximum range is about ten. Further, in accordance with a present technical level, it is expected that the lock range is allowed to be as narrow as possible to thereby construct a stable PLL circuit.
FIG. 2 is a view showing an image fluctuation phenomenon in the conventional processor shown in FIG. 1. An image display area 12 is displayed within a monitor 11. There is shown an image fluctuation state 13 in a vertical direction occurring in the case where the lower portion of the image display area 12 is expanded (enlarged) or contracted in a vertical direction.
FIG. 3 is a view similarly showing an image flicker phenomenon in the same conventional processor. Because of a jitter due to a phase fluctuation (frequency noise superimposed on a fixed frequency) of a line clock signal applied to the video memory 7, there takes place a line jumping phenomenon in a vertical direction with respect to the video memory 7. As a result, an image flicker 14 in the form of a lateral line appears on a monitor.
FIGS. 4 and 5 are views showing the relationship between line data in the video memory and a horizontal synchronizing signal or a line clock signal, respectively. The arrow of the line clock signal 19 indicates a timing or increment of a vertical address of the video memory 7, and the arrow of the horizontal synchronizing signal 18 shows a timing for establishing a vertical address (line position) incremented by the line clock 19. Here, explanation will be given on the assumption that lines 15, 18 and 17 are outputted from the video memory 7. In FIG. 4, the vertical address is incremented by one line at a timing indicated by the arrow of the line clock 19 after the arrow of the horizontal synchronizing signal 18, and that address is established at a timing indicated by the arrow of a next horizontal synchronizing signal 18. For this reason, lines 15, 18 and 17 are displayed in sequence. However, in FIG. 5, between the first arrow and the second arrow of the horizontal synchronizing signal 18, the arrow of the line clock signal 19 is inserted twice. Accordingly, before establishment of a vertical address by the second arrow of the horizontal synchronizing signal 18, increment of the vertical address is carried out twice. For this reason, line 17 might be read out at a timing where readout of the line 18 shown in FIG. 4 should be originally carried out, resulting in omission of display of the line 18. As stated above, when there exists a jitter on the line clock signal 19 the state of FIG. 4 and the state of FIG. 5 are repeatedly displayed. Thus, an image flicker 14 as shown in FIG. 3 would take place.
In this conventional processor, a vertical synchronizing signal of a low frequency of several tens Hertz (Hz) is used for the reference input terminal 1 (a) of the PEL circuit 9. Further, the set width of the frequency dividing value M of the frequency divider 8 is generally set to several tens to several thousands, thus to allow the lock range of the frequency divider 8 to be broad. For this reason, the design for constants of the loop filter 2 is not easy, and a large jitter appears on a line clock signal. As a result, there take place portions where jump of the vertical address with respect to the video memory is conducted and portions where no Jump is conducted, leading to an unseemly picture as an image flicker phenomenon in the form of a lateral line. It is generally difficult to precisely calculate a value of jitter because of various complicated conditions. Accordingly, when an actual measurement of jitter is conducted, a value oil 5 to 10 [.mu.S] was observed.
Further, every time alteration of the frequency dividing ratio M value for carrying out an expansion (enlargement) operation or a contraction operation of an image is made, expansion/contraction are repeated in a vertical direction by vibration based on a dumping factor .zeta. of the PLL circuit 9. Namely, for an acquisition time (time until a frequency difference is locked) of the PLL circuit 9, there results an unseemly picture as an image fluctuation phenomenon in a vertical direction.
Equations for calculating an acquisition time causing an image fluctuation phenomenon in a vertical direction are shown below.
When a control voltage width of VCO 3 is assumed as Vd [V], a gain constant K.PHI. of the phase comparator 1 is expressed as follows: EQU K.PHI.=(Vd/2)/2.pi.[V/rad] (1)
When an output frequency width of the VCO 3 is assumed as Fd [Hz], a conversion gain KV of the VCO 3 is expressed as follows: EQU KV=Fd.multidot.2.pi./Vd[rad/V.multidot.s] (2)
A loop gain K is expressed as follows: EQU K=K.PHI..multidot.KV (3)
In the case of an active filter, when .tau.1=C.R1, SQRT=SQUARE ROOT (.sqroot.), a natural angular frequency .omega.n is expressed as follow EQU .omega.n=SQRT(K/.tau.1 (4)
On the other hand, in the case where a general condition of .zeta.=O.7 V is selected, .omega.n.t becomes equal to about 4.5. Accordingly, the natural angular frequency .omega.n when the acquisition time is designated at t is expressed as follows: EQU .omega.n=4.5/t (5)
When substitution of Eq.(5) into Eq.(4) is made, the acquisition time t is expressed as follows: EQU t=SQRT(20.multidot..tau.1/K) (6)
It is seen that the acquisition time t is directly affected by the loop gain K. Accordingly, in the case where Vd in the loop gain K is assumed to be fixed, the acquisition time t is greatly affected by the output frequency width Fd of the VCO 3.